Switching power supply controllerSwitching Power Supply Abstract Switching Power Supply Claims 1. A switching power supply controller, wherein the switching power supply controller controls a plurality of pulse-width-modulated switching power supplies, comprising: a controller configured to control the pulse widths for each switching power supply to regulate the corresponding output from each switching power supply, the pulse widths for the switching power supplies being defined with respect to periods, and wherein the controller is further configured to control the pulse widths for each switching power supply in a given period based upon feedback information from each switching power supply in a previous period, and wherein the controller is further configured to store operating parameters associated with the switching power supplies and to calculate initial pulse widths based on the operating parameters for an initial period. 2. The switching power supply controller of claim 1, wherein the operating parameters include capacitances associated with each switching power supply. 3. The switching power supply controller of claim 1, wherein the operating parameters include an output voltage to be provided by the switching power supply. Switching Power Supply Description This invention relates to switching power supplies or converters. In particular, this invention relates to a simple, robust switching power supply which is capable of providing power to a number of different regulated power sources within a given circuit. BACKGROUND OF THE INVENTION Switching power supplies are used to provide power in numerous products such as cell phones, camera, PDAs (Personal Digital Assistants), calculators, portable computers and similar types of electronic equipment. Such switching power supplies are quite complex and use numerous components to provide a number of precisely regulated output voltages to power the various integrated circuits and other components contained within the product being powered. Relative to the cost and the quality of the products in which they are used, such power supplies are expensive, bulky and inefficient. Efficiency is important to provide the equipment a long battery life. FIG. 1 shows a typical prior art power supply used in portable equipment powered by a battery 10. The signal from battery 10 is transmitted on lead 10a to a level translation circuit 12, which is controlled by a control signal from analog pulse width modulated controller 11. The control signal from analog pulse width modulator is responsive to the voltage drop across resistor 16 as detected by signals on conductive leads 17a and 17b connecting, respectively, the two terminals of resistor 16 into analog PWM controller 11. N-channel MOS transistors 13a and 13b are connected to operate in a complementary fashion. Level translation circuit 12 provides a high level voltage to the gate of N-channel transistor 13a to apply a pulse from battery 10 to one input terminal of coil 15. The other input terminal of coil 15 is connected to one terminal of resistor 16. The other terminal of resistor 16 is connected to load capacitor 18, which contains a charge at the voltage necessary to supply the particular circuitry being powered by this portion of the power supply. The analog PWM controller 11 measures the current through resistor 16 and controls the ON time of N-channel MOS transistor 13a. N-channel MOS transistor 13b is driven by the complement of the signal driving the gate of N-channel MOS transistor 13a and turns on to pull the input lead of coil 15 to ground and to shut off the current required to be supplied through resistor 16 to the power supply. Internal circuitry of analog pulse width controller 11 is shown schematically in FIG. 2. As shown in FIG. 2, current source 20 provides a charging current to capacitor 21 to generate a ramp voltage across this capacitor. This ramp voltage is provided to the positive input lead of differential amplifier 22a, the negative input lead of which receives the output signal from differential amplifier 22b. The positive input lead of amplifier 22b is connected to the load capacitor 18 and carries a signal representing the voltage across the load capacitor 18. The negative input lead of differential amplifier 22b is connected to the node between resistors 23a and 23b making up a voltage divider (one terminal of which is connected to a reference voltage VRef and the other terminal of which is connected to the output lead of differential amplifier 22b). Thus when the output voltage across capacitor 18 is less than the voltage at node A between resistor 23a and resistor 23b, the output voltage from differential amplifier 22b goes to a low level. This low level output voltage is provided to the negative input lead of amplifier 22a, causing amplifier 22a to produce a positive output pulse. This positive output pulse is transferred to coil 15 to provide a charging current to capacitor 18. With time, the charge on capacitor 18 increases until the voltage across capacitor 18 exceeds the voltage on node A. At this point the output voltage from differential amplifier 22b goes to a high level, so that the voltage at the negative input lead of differential amplifier 22a exceeds the voltage on the positive input lead of differential amplifier 22a, causing the output voltage from amplifier 22a to go a low level, and thus preventing further charging of capacitor 18. The voltage across coil 15 is negative, reflecting the negative rate of change in current in response to the trailing edge of the pulse from amplifier 22a going from a high level to a low level. The current through coil 15 does not change instantaneously due to the magnetic field of the coil but rather gradually changes with time. This type of power supply, which is characterized by a current source driving a capacitor, is known as an analog buck converter. Each MOSFET modulation cycle is formed by the precision comparator and the error amplifier. Such a power supply is difficult to scale and integrate into an integrated circuit and is typically fabricated using dedicated analog process technologies at captive semiconductor foundries. Accordingly, what is needed is a power supply which provides different level precision voltages and at the same time and is simple to implement with a smaller number of components than in the prior art. Such a power supply must also be relatively inexpensive, robust and reliable. SUMMARY OF THE INVENTION In accordance with one embodiment of the present invention, a switching power supply controller is provided for controlling a plurality of pulse-width-modulated switching power supplies. The controller is configured to control the width of a pulse provided to each switching power supply in a period to regulate the output from the power supply. The width of a pulse to be provided to the power supply in a period is a function of feedback information from the power supply from a previous period. The controller stores operating parameters associated with the switching power supplies and calculates an initial pulse width to be applied to the power supplies for an initial period. In accordance with another embodiment, the operating parameters stored include capacitances associated with each switching power supply. In a further embodiment, the operating parameters include an output voltage to be provided by the switching power supplies. This invention will be more fully understood in conjunction with the drawings taken together with the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the basic construction of a prior art analog buck converter. FIG. 2 shows the details of the analog PWM controller 11 in FIG. 1. FIG. 3 shows the basic structure of a pulse width modulation controller utilizing a ring oscillator in accordance with this invention. FIG. 4 shows an alternative implementation of a pulse width modulated controller in accordance with this invention. FIG. 5 shows an example of waveforms of the type generated using the structure of FIG. 3. FIG. 6 shows a ring oscillator used in accordance with this invention together with a switching matrix used to select the particular output signals from the ring oscillator to be provided to the two input leads of an exclusive OR gate 63 to generate a pulse width modulated signal. FIG. 7 shows the waveform of signals generated using the structure of FIG. 6. FIG. 8 shows the waveforms generated using the structure of FIG. 6 with an inverter connected between the output lead from each even-numbered inverter in the ring oscillator and the pass-transistors driven by the signals G, H, I, J and K. FIG. 9 shows the relative delay times obtained when signals are selected from different combinations of pairs of inverters in the ring oscillator of FIG. 6. FIG. 10 shows one circuit for controlling the selection of the particular gates to transfer a selected pair of signals to the exclusive OR gate 63 in FIG. 6 to generate a pulse width modulated signal. FIG. 11 shows another circuit used to generate the pulse width modulated signal from exclusive OR gate 63 in FIG. 6 in accordance with the principles of this invention FIG. 12 is a block diagram of switching power supply controller 1200, in accordance with one embodiment of the present invention. FIG. 13 is a block diagram showing interface signals of digital pulse converter wrapper 1201, according to one implementation. FIG. 14 is a block diagram showing interface signals of analog to digital converter 1206, according to one implementation. FIG. 15 is a block diagram showing the interface signals of Kelvin temperature sensor (KTS) 1500. FIG. 15A is an exemplary circuit for KTS 1500 in accordance with one implementation. FIG. 16 is a timing diagram illustrating the quad-slope (i.e., dual conversion) analog to digital conversion (ADC) operations carried out in the QSADC module 1211a, which is contained within touch screen interface 1211. FIG. 17 is a block diagram showing the interface signals of QSADC module 1211a in one implementation. FIG. 17A is a block diagram showing the interface signals of QSADC 1211a with touch screen interface 1211 in one implementation. FIG. 18 is a top-level block diagram of QSADC module 1211a, including analog block ANLG 1801, control block CNTRL 1802 and DOWN/UP COUNTER block 1803, according to one embodiment of the present invention. FIG. 18A shows one implementation of analog block 1801 of QSAD module 1211a shown in FIG. 18. FIG. 18B shows one arrangement of a four-contact touch-screen application. FIG. 18C shows one arrangement of a five-contact touch-screen application. FIG. 19 is a block diagram summarizing the modules in switching power supply controller 1200, providing a control loop for a battery or power supply management application. FIG. 20 illustrates regulation of output voltage Vout using inductor current IL and sensing output voltage Vout, according to one embodiment of the present invention. FIG. 21 illustrates the approximation of a weighted average inductor current by duty cycle. FIG. 22 illustrates a method under the present invention for estimating the parasitic resistance of an MOS switch. FIG. 23 shows flow diagram 2300, illustrating a control method according to one embodiment of the present invention. FIG. 24 illustrates a low-frequency closed loop and high-frequency open loop control method, according to one embodiment of the present invention. FIG. 25 is a diagram showing switching power supply controller 1200 being used in a battery and power supply management application in, for example, a personal digital assistant (PDA). FIG. 26 illustrates the operation of a control loop in accordance of the present invention. FIG. 27 illustrates the low-frequency closed loop and high-frequency open loop control method of FIG. 24, showing the signature input values of controlled variables and an open-loop response, according to one embodiment of the present invention. FIG. 28 illustrates a sequential transient recovery control method, in accordance with one embodiment of the present invention. FIG. 29 illustrates a buck converter. FIG. 30 through FIG. 33 show curves of current with respect to time for a supply circuit such as circuit 49, based on the application of different gate drive voltages to the transistors. FIG. 34 is a block diagram showing the interface signals of clock generator 12223. FIG. 35 shows the port table for the clock generator block shown in FIG. 34 and FIG. 12. FIG. 36 shows an exemplary pulse width modulation implementation, which includes a pulse width generator and a sequencer, for digital pulse converter 1201. FIG. 36A is an exemplary implementation of the pulse width generator of FIG. 36. FIG. 36B is an exemplary implementation of the sequencer of FIG. 36. FIG. 36C shows an exemplary feedback control system. FIG. 36D shows another exemplary feedback control system. FIG. 37 shows a timing diagram for one digital to pulse converter frame for DPC 1201 in accordance with one implementation. FIG. 37A shows exemplary interface signals for digital pulse converter 1201 for one implementation. FIG. 37B illustrates an exemplary circuit implementation for DPC 1201, which includes a CAM. FIG. 37C illustrates one exemplary implementation for the CAM of FIG. 37B. FIG. 37D illustrates an exemplary circuit implementation for output logic of the CAM of FIG. 37C. FIG. 37E illustrates an exemplary timing diagram for the CAM of FIG. 37C. FIG. 38 shows an exemplary implementation of a Grey counter. FIG. 38A shows another exemplary implementation of a Grey counter. FIG. 38B shows an exemplary implementation for a flip flop of FIG. 38 or FIG. 38A. FIG. 38C shows an exemplary implementation for another flip flop of FIG. 38 or FIG. 38A. FIG. 38D shows an exemplary circuit implementation for a logic gate. FIG. 38E shows an exemplary circuit implementation for another logic gate. FIG. 38F shows an exemplary circuit implementation for a multiplexer. FIG. 38G shows an exemplary circuit implementation for binary to Grey and Grey to binary conversion. FIG. 38H illustrates an exemplary implementation for a digital pulse converter. FIG. 38I illustrates another exemplary implementation for a digital pulse converter. FIG. 39 shows a plot of typical gate drive waveforms which may be applied to, for example, the gates of the transistors of circuit 49 and the resulting voltage at terminal S. FIG. 40 is a block diagram of SHM 1207 in one implementation. FIG. 40A is a functional schematic illustrating voltage and current sampling for one implementation. FIG. 40B is a circuit schematic illustrating voltage and current selection for one implementation. FIG. 40C is an exemplary interface signal block for SHM 1207 in accordance with another implementation. FIG. 40D is a block diagram of SHM 1207 in another implementation. FIG. 40E is a functional schematic illustrating voltage and current sampling for another implementation. FIG. 40F is a circuit schematic illustrating voltage and current selection for another implementation. FIG. 40G is a clock generation circuit in accordance with another implementation. FIG. 40H is a voltage divider in accordance with another implementation. FIG. 40I is a voltage multiplier in accordance with another implementation. FIG. 40J is an exemplary interface signal block for an I/O circuit in accordance with another implementation. FIG. 40K is a multiplexer scheme in accordance with another implementation. FIG. 41 is a block diagram of the regulation control module (REG) of FIG. 12 according to one embodiment of the invention. FIG. 42 shows a gate drive waveform with respect to time. FIG. 42A shows a boost converter circuit. FIG. 42B shows two switching waveform in time off-set relationship. FIG. 43 shows waveform A, B and C illustrating the current which is output for three gate drive scenarios of a switching power supply. FIG. 43A shows a plot of the voltage with respect to time at a terminal S intermediate the upper and lower transistors in buck converter 49 of FIG. 29. FIG. 43B and FIG. 43C show plots of the voltage at terminal S for two different duty cycles of FET 50 in circuit 49. FIG. 44 shows a circuit for generating a high voltage to drive a cold cathode fluorescent light bulb. FIG. 44A shows two exemplary sets of gate drive waveforms of the type which could be applied to the gates of the transistors of circuit 1.2.2.12. FIG. 45 shows a buck converter circuit. FIG. 45A shows gate drive waveforms for the transistors in FIG. 45 and corresponding current and output voltage waveforms. FIG. 45B shows a boost circuit. FIG. 45C shows gate drive waveforms for the circuit of FIG. 45B and corresponding current and output voltage waveforms. FIG. 46 shows switching power supply controller 1200 connected to regulate the operation of two switching power supplies. FIG. 46A shows a plot of current with respect to time for one cycle of a switching power supply. FIG. 46B shows a buck power supply circuit. FIG. 46C shows a plot of current with respect to time for one cycle of a switching power supply circuit. FIG. 46D shows a plot of current with respect to time for one cycle of a switching power supply. FIG. 46E shows a plot of current with respect to time for a switching power supply circuit. FIG. 47 shows switching power supply controller 1200 connected to a plurality of power supplies. FIG. 48 shows in block diagram form a processor coupled to two switching supplies, a nonvolatile memory and a Kelvin temperature sensor, with a battery connected to one of the switching power supplies. FIG. 48A shows a curve of battery capacity with respect to temperature for a typical battery. FIG. 49 shows a block diagram of a power supply system for use in conjunction with a cellular telephone. FIG. 49A shows a block diagram for a solar cell array coupled to a power supply being controlled by switching power supply controller 1200 of the present invention. FIG. 50 is a block diagram of a spreader divider unit 2482.4 according to one embodiment of the invention. FIG. 50A is a circuit diagram of a spectral spreader 210.1 for the spreader divider unit 2482.4 of FIG. 50 according to one embodiment of the invention. FIG. 51 is a block diagram showing the interface signals of QSADC module 1211b in another implementation. FIG. 51A is a top-level block diagram of QSADC module 1211b, including analog block 2001.4, control block 2002.4, and up/down counter block 2003.4, according to another embodiment of the present invention. FIG. 51B shows one implementation of analog block 2001.4 of FIG. 51A. FIG. 51C illustrates a block diagram showing exemplary interface signals between touch screen interface 1211 and the other blocks of switching power supply controller 1200. FIG. 51D shows a flowchart for performing diagnostics of QSADC module 1211a. FIG. 51E shows a functional block diagram corresponding to the implementation of FIG. 51B. FIG. 51F illustrates the circuit connections of analog block 1801 for an initial measurement state. FIG. 51G illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the Y coordinate sheet in a four-contact implementation. FIG. 51H illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the Y coordinate sheet in a four-contact implementation. FIG. 51I illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the X coordinate sheet in a four-contact implementation. FIG. 51J illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the X coordinate sheet in a four-contact implementation. FIG. 51K illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to horizontal position. FIG. 51L illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to vertical position. FIG. 51M illustrates the circuit connections of analog block 1801 to integrate the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to horizontal position. FIG. 51N illustrates the circuit connections of analog block 1801 to digitally convert the voltage due to contact with the X-Y coordinate sheet in a five-contact implementation due to horizontal position. FIG. 51O illustrates the circuit connections of analog block 1801 to detect continuity between the resistive sheets in a four-contact implementation. FIG. 51P illustrates the detection of contact for a five-contact implementation. FIG. 52 illustrates a block diagram of LED control block 1214. FIG. 53 is a block diagram for the watchdog module of FIG. 12 according to one embodiment of the invention. FIG. 54 is an exemplary functional diagram of Internal Voltage Supply (IVS) 1209 in accordance with one implementation. FIG. 54A is an exemplary interface block diagram for IVS 1209 in accordance with another implementation. FIG. 54B is another exemplary functional diagram of IVS 1209 in accordance with another implementation. FIG. 54C is an exemplary flowchart for a power-up sequence for IVS 1209 in accordance with another implementation. FIG. 55 is an exemplary functional diagram of NFET driver module 1202 in accordance with one implementation. FIG. 55A illustrates exemplary interface signals of NFET driver module 1202 in accordance with another implementation. FIG. 55B illustrates exemplary interface signals of NFET driver module 1202 in accordance with another implementation. FIG. 55C shows an exemplary functional diagram for the implementation of FIG. 55B. FIG. 55D illustrates an application employing internal buffers to directly drive an external coil for the implementation of FIG. 55B. FIG. 55E illustrates an application employing internal buffers to drive external FETs for the implementation of FIG. 55B. FIG. 55F shows an exemplary on-chip configuration block diagram for the implementation of FIG. 55B. FIG. 56 is a block diagram of central processing module (SYS) 1205 of FIG. 12 according to one embodiment of the invention. FIG. 57 shows a circuit model of converter 2570 of FIG. 25. FIG. 58 is a flow chart illustrating the steps of control algorithm 5800, in accordance to with one embodiment of the present invention. FIG. 59 illustrates the operation of control algorithm 5800 of FIG. 58. DETAILED DESCRIPTION OF THE EMBODIMENT(S) The following detailed description is intended to illustrate the embodiments discussed herein and is not intended to be limiting of the scope of the present invention. Other embodiments of this invention will be apparent to those skilled in the art in view of this disclosure. Section 1.0 Overview of the Architecture of a Converter (Digitally Trimmed Multi-stage SPS) having a Synchronous Sampling Multiple-output Controller, Functional Description of Each Block The present invention is applicable to a power converter and power management peripheral that integrates a set of power-management related functions. Switching power supply controller 1200, shown in FIG. 12 in block diagram form, illustrates an implementation of a switching power converter controller product, according to one embodiment of the present invention. The system implements substantially all of a power converter's expected functions, such as maintaining a steady output voltage (constant voltage power supply) that is substantially independent of the current drawn from the power supply or maintaining a steady output current (constant current power supply) that is substantially independent on the load applied to the power supply, deciding when to shed loads, and measuring the state of charge in a battery, charging the battery, and performing battery sequencing. In addition, the system performs a number of other peripheral management functions, such as digitizing a touch panel, scanning a keyboard, and conditioning reset signals received from the rest of the system. In one embodiment, watch dog timer functions are provided to allow power-cycling and to provide reset signals to different subsystems of the product, in response to an exception condition, such as a software lock up or even a hardware lock up (e.g., an SCR latch up or a disruption due to an IO transient). The system of the present invention also controls LEDs that indicates the statuses of various subsystems. Thus, a system according to the present invention can handle a large number of functions that a portable electronic device (e.g., a PDA) performs when the processor of that PDA is powered down, such as between pen strokes (while the user is writing a note on the PDA), or when the PDA is displaying information, but no input or output is expected. In this implementation, the product includes a digital control subsystem that controls various digital interfaces, including reset signals, watch dog timers, enable signals, status signals for indicating individual status of internal power supplies. Communication among elements of the system is provided through a communication interface. In one embodiment, the present invention includes a time base generation circuit and a digitizer interface to a keyboard. Referring to FIG. 12, substantially all of the digital interface functions are performed by an internal 8051 or a comparable microprocessor which is included in central processing module (SYS) 1205 and which communicates with the outside system with a number of interfaces through a number of general purpose input/output (GPIO) signals that can be defined in software in the microprocessor and mapped flexibly to individual input or output pins or terminals of the integrated circuit. For example, each pin can be defined to carry a high true or a low true signal, and can be defined to be an input signal or an output signal. In addition, each pin can be assigned to any of the individual power supply elements and can be shared so that more than one power supply can receive the same control signal from a single pin. In this manner, for example, a single enable signal may be shared amongst multiple power supplies. The GPIO signals can be used to implement input and output signals of some of the peripheral devices. For example, the keyboard scanner functions interact with an external keyboard through the GPIO signal interface. The watch-dog timer may receive input signals and status information from circuits external to the integrated circuit. Also, interrupt signals can share pins with the GPIO signals. This implementation thus provides a rich set of functionality to allow the product to be capable of being made "plug-compatible" with prior art solutions that were based on separate discrete devices. Central processing module (SYS) 1205 handles serial communication on and off the chip. Every signal which can be implemented as a GPIO signal, except an interrupt signal, can also be implemented as a serial communication signal. In an application designed for prior art devices, serial communication can be used to access a keyboard and coulombmetric measurement capabilities. The GPIO signals can be used to turn on and off individual power supplies and to monitor their statuses. A computation circuit, which may be provided as a very long instruction word processor ("VLIW engine") to simplify decoding logic, is included in regulation control module (REG) 1204 (labelled in FIG. 12 as "REG"). The VLIW engine executes low level commands from central processing module (SYS) 1205 (labeled in FIG. 12 as "SYS"). Regulation control module (REG) 1204 receives and interprets the measurements of voltages and currents from the various circuits supplied by the regulated power supply pins. Using a number of different types of control loops, regulation control module (REG) 1204 provides to digital pulse converter (DPC) 1201 commands in the form of precisely modulated signals, which then are used to operate external components through NFET driver module 1202. Together with the external components, switching power supply controller 1200 forms one or more power converters of various designated topologies. One unique feature of the system according to the present invention is that the system is programmable. In addition to allowing every function, mode and regulation parameters to be preset, the specifications of external components can be stored internally in the integrated circuit and used to perform the regulator functions. Thus, regulation control module (REG) 1204 operates with a large amount of information about the characteristics of the power converter components external to switching power supply controller 1200. Unlike a prior art switching power supply controller circuit implemented in analog technology, a power supply controller circuit of the present invention "knows" the output voltage it's trying to attain ("target voltage") and the error (i.e., the difference between the current output voltage and the target voltage). Typically, prior art analog converters correct the error using algorithms that are independent of the current switching duty cycle or the value of the input voltage. Such prior art converters also do not internally store information about the external components. An engineer attempting to design with such a prior art power supply controller circuit can only provide "hints" to the power supply controller circuit in the form of compensation networks. In contrast, a power supply controller circuit according to the present invention has many advantages and benefits over the prior. For example, having information regarding the current output voltage and duty cycle, the target voltage and the internally stored parameter values of the external circuit allows the power supply controller to calculate the potential duty cycles that would result in the correct output voltage to high precision and to select a realistic response that observes the constraints of the external circuit (e.g., the saturation current of an inductor). Proper response to external circuit anomaly limits the amount of noise that's reflected to the power supply controller circuit. For example, by controlling the transient noise currents through the power controller circuit, a battery or a long wire that provide the supply voltage to the power controller circuit could experience and possibly radiate less electromagnetic interference (EMI). A programmable keyboard scan function is implemented in central processing module (SYS) 1205, and allows individual keys to be scanned or detected after a key has been pressed to awake the keyboard scanning circuit from a stand-by state. A watch dog function is performed with software in central processing module (SYS) 1205, and provides full-featured watch-dog timer functions. Watch dog timer functions may be used to handle software faults in a system. For example an external processor running a complex operating system (e.g., Win CE) may periodically briefly assert ("toggle") a signal on a specified pin. The watch dog timer resets its timer whenever the signal on the specified pin is toggled. When a malfunction occurs in the software of the host microprocessor, such that the signal on the specified pin is not toggled within the scheduled time, then a set of pre-programmed actions are taken to recover operation of the external system processor. These actions range from simply resetting the processor or another circuit element, or cycling the processor's power off and on. Power-cycling removes current from parasitic SCRs that may be present in the processor or other integrated circuits, thereby affecting a recovery from a semiconductor latch-up state. Other anomalies that would normally not be recoverable using logic or reset signals may also be corrected through power cycling. Central processing module (SYS) 1205 controls external status LEDs, or a single multi-color LED. Internal reset logic which is included in internal voltage supply 1209, provides a power-on reset to allow internal clocks and internally generated voltages to stabilize prior to operation. This is a different and distinct concept from the host reset conditioning feature described below, which is implemented in software and runs on the internal microcontroller. The host reset conditioning software conditions the external system's reset signal with the status signals of the power supplies, and external signals at the product's input pins. Touch screen interface 1211 uses a dual-slope technique to read the X and Y coordinates of a resistive touch panel display. In a PDA, this digitization operation, because of the large area of the display, is quite subject to noise induced by the back light. In the prior art, a typical back light is implemented by cold cathode fluorescent light (CCFL), which is essentially a fluorescent light bulb that does not have a cathode heater to raise the energy of the internal gas for ionization at a low voltage. In CCFL, for a typical device, initial ionization ("ignition") is brought about using an AC voltage of 700 volts or more, and an AC voltage of over 300 volts is used thereafter to maintain the ignition. The high voltage AC waveform that is driving the CCFL is a potentially serious source of noise to the touch panel, which is made up of panels of resistive material and is located only a few millimeters away directly in front of the display. Touch screen interface 1211 uses a quad-slope analog-to-digital converter circuit which operates synchronously with the back light voltages generated by the power supply controller. By operating synchronously with the back light, the noise from the back light is integrated over an even number of cycles, thereby effectively removing it without a of complex filtering or an algorithmic approach. Internal voltage supply 1209 is the power supply for switching power supply controller 1200, deriving from either one of two external supply pins, or one of two external battery pins the internal voltages required for the operations of the various blocks, including central processing module (SYS) 1205 and regulation control module (REG) 1204. In addition to providing the various voltages required for the various subsystems, internal voltage supply 1209 also provides the crystal oscillator function (other than the crystal, which is off-chip) various charge pumps for creating internal supplies, and comparators to indicate when the supplies are stable for use by internal processing elements. Sample and hold module 1207 includes an array of sample and hold circuits and scaling circuits. Sample and hold module 1207 monitors the various points within the output sections of the power supplies, measuring voltages and currents, input voltages, and temperatures at various points. Sample and hold module 1207 provides its data, one sample at a time, to analog to digital converter 1206 (a system shared resource), which converts the external analog samples into digital samples. The digital samples are used by regulation control module (REG) 1204, or passed upstream to central processing module (SYS) 1205. In this embodiment of the present invention, the analog to digital converter and the sample and hold structures are based on either ratios of capacitors or unity gain. Thus, calibration can be achieved using a single calibration. NFET drivers module 1202 include a set of output drivers which operate in one of two modes. The first mode is to drive external power MOSFET devices. In this mode, each output voltage is associated with two sets of driver circuits; one for driving the control FET and the other one for driving the sync FET. For modest currents, the two driver circuits may be used in another mode of operation where they are driven together, and their output signals may be connected together, to drive an external coil directly in a power switching function. A power supply utilizing the present invention can be completely programmable, i.e., no external discrete components have to be chosen to set voltages and currents and a single chip can perform many different functions across many different products. Such programmability has the benefit of reducing the component count on a circuit board. It also has the benefit of reducing the number of parts that an individual manufacturer of an end product would have to stock since this same device can be used across many different applications. All of these features can be preset, either at the time the chip is manufactured, at the time that it is delivered, i.e., through a distributor, using programming techniques similar to those used with programmable logic array devices. Alternatively, the system of the present invention can be programmed by a customer even on the circuit board during the in-circuit test phase or final test for their product. Further, even though all these functions can be programmed, the values programmed during manufacturing and test are used merely as initial conditions and may be changed dynamically (i.e., during operation) by the system containing the power supply controller. For example, the system can reprogram the internal voltages and currents dynamically, as is often required in complex microprocessors which require different voltages for different modes of operation. Reprogramming activity can also be done for the purposes of dimming displays and controlling motors. Digital-to-analog conversion functions can be implemented by rapidly changing the output voltages of the regulators. Switching power supply controller 1200 features a completely programmable start-up and shut-down sequence, so as to allow a system using power supply controller 1200 to be started in a sequence that would avoid a latch-up conditions. For example, the I/O structure of a microprocessor is often required be powered before the microprocessor core. To reverse the order could result in damage or destruction of the microprocessor or cause a malfunction. A specific power sequence is also required for powering down these devices. In prior art solutions, this timing is set rather crudely by resistors and capacitors or not at all. The individual power supplies controlled by switching power supply controller 1200 can be programmed for a wide variety of topologies, so that if a voltage which is higher than the input source, lower than the input source, or sometimes the same as the input source can be accommodated. For example, a boost converter topology is used for a power supply having an output voltage that is higher than the input voltage, a buck converter topology is used for a power supply having an output voltage that is lower case than the input voltage, and a sepic topology is used for a power supply having the same input and output voltages. When very high voltages are required (i.e., a cold cathode fluorescent light bulb or even a photographic strobe in a digital camera), topologies such as half-bridge may be used. All of these can be programmed and any number of them can be present in the design at any time, and any combination of these topologies may be supported simultaneously. Switching power supply controller 1200 of the present invention can also perform dimming using pulse width modulation. This ability is important for cold cathode fluorescent lights because, typically, a simple reduction of current provides insufficient energy to ionize the entire display, resulting in the so called "thermometer effect" where only part of the back light is actually illuminated. Another application where PWM dimming is desirable is in white LEDs. White LEDs suffer an esthetically unacceptable shift in hue or color, as a function of current. Using pulse-width modulation for dimming white LEDs maintains a constant current during "on" time, so that a constant color is maintained over a large dimming range. Switching power supply controller 1200 also has input pins for use in temperature compensation: an internal temperature sensor is included, as well as external pins for reading an external temperature sensor. Temperature compensation is used in battery-charging to tailor a rate of charge, to respond to unsafe environmental conditions, to detect fault conditions and to prevent the destruction of external batteries or damage due to excessive heat build-up. The internal battery charger algorithms accommodate a number of different chemistries (e.g., lithium ion). Any chemistry can be accommodated since battery charging algorithms are provided in software to be executed in central processing module (SYS) 1205. Switching power supply controller 1200 also allows selection between different batteries as its power supply. Central processing module (SYS) 1205 can be programmed to use an external battery first, thus preserving its internal battery for emergency situations or while the external battery is being changed. It can also automatically choose to charge the internal battery first, and then external accessory batteries second. Central processing module (SYS) 1205 computes how much energy is available and charge both batteries at the same time or use them in parallel. Another function provided by a product using the present invention is the ability to provide the voltage, current and coulombmetric data to the outside system. This permits independent direct control over the voltage regulator functions and intermediate readings of the amount of energy available in a battery before an individual threshold. A system encompassing the present invention also maintains a charge acceptance history. This is useful in determining whether the battery may be fully charged. It's also an early indicator of battery wear out and provides a basis for limiting overcharge events where the battery may be indefinitely charged because of some sort of malfunction. In accordance with one aspect of the present invention, the individual switching waveforms of the product are carefully staggered so that the amount of energy that is derived from an external power source, for example, a battery, is made as uniform as possible around all of the different outputs that require power. This effectively raises the frequency of the current required from the external source and may reduce the peak current demanded from an external source, which reduces the amount of noise on that external source and also reduces the noise radiated from the interconnecting wires to the external source and makes the noise easier to filter. Additionally, a spread spectrum approach is applied to internal frequencies. This reduces the net energy at a given frequency from external switching power supply functions. That is to say that instead of always operating at a constant frequency, the spread spectrum feature allows the switching frequency to be varied rapidly and that frequency modulated using industry standard patterns so that the energy at any particular frequency is reduced. The spread spectrum feature effectively reduces noise that would be experienced by an associated radio either within a product using the present invention, within the end product that this chip is implemented within or other products that are nearby. The frequency of operation can also be determined by external sources. In one embodiment, a 32 kilohertz crystal oscillator generates all the internal clocks and provides a 32 kilohertz time based output for use by other elements within the system. According to another feature, the system provides an external clock which is guaranteed to be 20 nanoseconds away from the nearest switching edge. This unique feature allows the external system to conduct sampling synchronously with the switching power supply functions in the same way the system synchronously samples to reduce switching noise internally. Normal switching prior art switching power supplies, since they have no knowledge of what duty cycle they're going to provide in any given cycle, have no way to provide this information ahead of time. Since all of the pulse width modulators used in the present invention are digital, this is achieved by another control signal that is scheduled within the array of control signals that make up all the pulse width modulators. Referring to FIG. 12, clock generator macro 1223 (CLKGEN) generates clock signals required by the modules illustrated in FIG. 12. The clock generator module 1223 is illustrated in greater detail in the high level block diagram of FIG. 34 which shows the interface signals. The clock generator generates the clocks based on a source clock signals provided by digital pulse control module 1201. These source clock pulses are received by clock generator module 1223 over CST[9:0] output bus 1223.2 and the output ports PLOCK and PLLCK from DPC 1201 which are provided on interfaces 1223.4 and 1223.1, respectively. In the table below, the frequencies of the signals on the CST bus 1223.2 are illustrated. Referring to the various interfaces to clock generator 1223, the CST interface from DPC module 1201 is comprised of a 10-bit bus indicated by reference character 1223.2 and FIG. 34. The bus is connected to the output of the GREY counter in DPC 1201 and provides the majority of the source clocks for clock generator 1223. Table 102A shows the frequency of the signals on each of the bus lines CST[0] to CST[9]. TABLE 102A CST Bit Frequency khz CST [0] 134,217.728 CST [1] 67,108.864 CST [2] 33,554.432 CST [3] 16,777.216 CST [4] 8,388.608 CST [5] 4,194.304 CST [6] 2,097.152 CST [7] 1,048.576 CST [8] 524.288 CST [9] 524.288 The 2-bit bus PD_OUT[1:0] indicated by reference character 1223.3 controls the mode of operation of the generated clock signals. Power modes of operation are designated as Standard, Low Power and Shut Down. Table 102B below shows the modes as function of the signals on the 2-bit bus. TABLE 102B PD_OUT [1] PD_OUT [0] Mode 0 0 Shut Down 0 1 TBD 1 0 Low Power 1 1 Standard The clock signal to analog to digital converter 1206 is provided over line 1223.7 and the frequencies at the various modes are indicated as set forth below in Table 102C. The Low Power and Standard mode frequencies are derived from the 538,870.921 khz DPLL clock through a division by 5. TABLE 102C Mode Frequency (khz) Shut Down 0 Low Power 107,374.1824 Standard 107,374.1824 The clock signal to the sample and hold block 1207 is provided over line 1223.9. The frequency which is needed for the various modes of operation is shown in Table 102D below. The Standard mode frequency is derived from bit CST[4] bit, and the Low Power mode frequency is derived from a division of the CST[8] bit by 2. TABLE 102D Mode Frequency (khz) Shut Down 0 Low Power 262.144 Standard 8,388.608 The clock signal to the internal voltage supply 1209 is provided over line 1223.8 and the frequencies needed for the various modes of operation are illustrated in Table 102E below. The Standard mode frequency is derived from the CST[4] that, in the Low Power mode frequency is derived by the division of the CST[8] bit by 2. TABLE 102E Mode Frequency (khz) Shut Down 0 Low Power 1,048.576 Standard 0 The clock signals for touch screen interface 1211 are provided by the QSADC_CLK. The frequencies for the various modes of operations are shown in Table 102F below. The Low Power and Standard mode frequencies are derived from the CST[8] bit through a division by 2. TABLE 102F Mode Frequency (khz) Shut Down 0 Low Power 262,144 Standard 262,144 Regulation control module (REG) 1204 is provided clock signals for the Standard, Low Power and Shut Down modes by the clock generator 1223, and the frequency for each is indicated in Table 102G below. The frequencies for the various modes are derived, for example the Standard mode by using CST[0] bit and the low power operating frequency is derived from bit CST[8] through a division by 4. In addition, CLKGEN 1223 provides the SHM CLK and SYS CLK clock signals to regulation control module (REG) 1204. TABLE 102G Mode Frequency (khz) Shut Down 0 Low Power 131.072 Standard 134,217.728 Table 102H illustrates the modes and frequencies for those modes for the clock signal provided to central processing module (SYS) 1205. As illustrated in Table 102H, in the Shut Down mode the frequency is 0. For the Low Power and Standard modes, the frequencies are identical and they are derived from CST[2]. TABLE 102H Mode Frequency (khz) Shut Down 0 Low Power 33,554.432 Standard 33,554.432 The LED_CLK is a clock used for the LED block which is associated with central processing module (SYS) 1205. The frequencies for the various modes of operation are indicated in Table 102I below. The Standard Mode frequency is derived from the CST[8] through a division by 2. TABLE 102I Mode Frequency (khz) Shut Down 0 Low Power 0 Standard 262.144 A digital supply voltage of 3.3 V.+-.300 mV is provided to clock generator block 1223 via VDD which is connected to the core digital power supply. Similarly, VSS is provided over line 1223.6 and is the core digital ground. Turning to FIG. 35, the port table is illustrated showing the port names, whether it is an input or an output, the description as well as the source and destination of the signals for those ports. Referring to FIG. 12, reset circuit 1221 generates the resets for switching power supply controller 1200. The signals received by this circuit and produced by the circuit are indicated within the block. As with the other circuits shown in FIG. 12, the arrow adjacent to the signal name indicates whether the signal is generated by or received by reset circuit 1221. Section 1.1 Detailed Descriptions of the DPC and Operation, Alternative Implementations Digital Pulse Converter wrapper 1201 can be implemented as a combination of a custom mixed-signal circuit (DPC) and an interface wrapper of digital glue logic synthesized from a logic circuit description expressed in a hardware description language (HDL). In this implementation, digital pulse converter wrapper 1201 converts 10-bit digital values to pulses with edges resolved to about 2 ns. As explained in further detail below, dual-port memory block with a single write port and a single read port is provided to store 10-bit values that express pulse start and width control, cycle skipping and bypass circuitry control (for direct output control). FIG. 13 is a block diagram showing interface signals of digital pulse converter wrapper 1201, according to one implementation. As shown in FIG. 13, digital pulse converter wrapper 1201 has five interfaces: (a) timing control interface 1301, (b) regulation control interface 1302, (c) power regulation interface 1303, (d) sample and hold control interface 1304, and (e) power supply interface 1305. Timing control interface 1301 includes 32 KHz, 50% duty cycle reference clock signal 1301a (FREF), reference clock bypass control signal 1301b (BYPASS), digital phase-locked status signal 1301c (PLOCK), count time state bus 1301d (CS[9:0]), and output state bus 1301e (STATE[15:0]), which are used to provide clocks and control states for the circuitry external digital pulse converter wrapper 1201. In this implementation, reference clock signal 1301a (i.e., signal FREF) is a reference clock provided to a digital phase-locked loop (DPLL) in digital pulse converter wrapper 1201 for frequency synthesis, and bypass controls signal 1301b (i.e., the BYPASS signal) is a test control signal used for bypassing the DPLL. PLOCK is a status signal indicating a phase-locked condition of reference clock signal 1301a in the DPLL. Count time state bus 1301d (i.e., bus CS[9:0]) is a 10-bit clock state bus which provides the clocks and control states to synchronize the DPC, the interface and other core circuits of switching power supply controller 1200. While count time state bus 1301d collectively displays the time state of the DPC, individual bits of count time state bus 1301d can be used as 50% duty cycle clocks. For example, if a 31.25 KHz reference clock is used, bit CS[9] corresponds to a 256 KHz clock with a 50% duty cycle, bit CS[8] corresponds to a 512 KHz clock with a 50% duty cycle. In general CS[n] corresponds to a 50% duty cycle clock with frequency f(n,m)=2.sup.-(n+m) f.sub.0, where n .epsilon. {0, 1, . . . , 9} and m .epsilon. {0, 1, . . . , 6}. Output state bus 1301e (i.e., bus STATE[15:0]) is a 16-bit state bus which displays the internal state of switch control buses 1303a and 1303b (described below) prior to passing through the direct control logic used by regulation control interface 1303 to force the output signals of switch control bus 1303a (i.e., HIGHFET) and switch control bus (i.e., LOWFET) to specific states. Bus 1301e signals when write operations can occur to the DPC core circuit. Regulation control interface 1302, which provides access to the dual-port memory in digital pulse converter wrapper 1201, includes memory write data bus 1302a (DWI[9:0]), memory address bus 1302b (ADW[7:0]), memory read data bus 1302c (DWO[9:0]), write-enable signal 1302d (WE) and read-enable signal 1302e (RE). Regulation control interface 1302 controls the offsets and pulse widths for the various pulses in power regulation interface 1303. Power regulation interface 1303 includes switch control bus 1303a (HIGHFET[6:0]) and switch control bus 1303b (LOWFET[6:0]). Sample and hold control interface 1304, which controls the sampling and holding of analog voltages for digital conversion by the ADC used in the system control loop, includes a first sample control bus 1304a (SMPA[6:0]), a second sample control bus 1304b (SMPB[6:0]), and an auxiliary control bus 1304c (SMPAX[3:0]). The timing for each bit in the sample buses 1304a and 1304b is associated with each bit of the corresponding switch bus 1303a or switch bus 1303b. Each of sample buses 1304a and 1034b controls the sampling and holding of analog voltages associated with either the HIGHFET or LOWFET control buses for digital conversion. Sampling control bus 1304c (i.e., auxiliary sample SMPAX[3:0]) controls the sampling of other analog signals needed for system monitoring and control. Power supply interface 1305 includes digital power reference 1305c (VDD), analog power reference 1305d (AVD), digital ground reference 1305a (VSS) and analog ground reference 1305b (AVS). Digital power and ground reference signals (i.e., VDD and VSS references) are global signals. In this implementation, VDD is the digital high voltage supply (3.3 V.+-.10%) connected to the core digital power supply. AVD is the analog high voltage supply (3.3 V.+-.10%) connected to the core analog power supply. VSS and AVS are, respectively, the digital ground and analog ground references (0V) connected to the core digital ground reference. Section 1.1.1 First Embodiment of PWM Timing Generator FIG. 3 shows a supply management controller of a type in accordance with this invention. As shown in FIG. 3, a ring oscillator includes inverters 301-1 through 301-15 connected in series. In an actual embodiment of this invention, the ring oscillator may include a larger number of series-connected inverters. For example, a thousand inverters can be connected in series, with the result that the duty cycle achieved by the controller of this invention can be almost 100%. However, to simplify explanation, only 15 inverters will be illustrated in this detailed description. The inverters each have inherently a delay ".DELTA.," which is the elapsed time between the time a signal is applied to the input lead to the inverter and the time the resulting output signal is obtained on the output lead of each inverter. This time ".DELTA." is a function of the voltage applied to the components contained within the inverter. By varying the voltage applied to the inverter's components, the actual delay time .DELTA. associated with an inverter can be varied. A typical inverter in CMOS technology will contain a P-channel MOS device series connected with an N-channel MOS device between a voltage source and a reference voltage, typically system ground. Should buffers be used with an inverter an additional four transistors may be used giving each inverter six transistors. The delay associated with the transmission of a signal through the inverter is a function of the voltage applied to the inverter. The higher the supply voltage applied to the inverter, the slower the transmission of the signal from the input to the output lead and the larger the delay .DELTA.. In the structure of FIG. 3 a crystal 302 capable of oscillating at 32.768 KHz is connected by leads 303a and 303b to an inverting amplifier 304. Amplifier 304 provides a voltage across the crystal to cause the crystal to oscillate at 32.768 KHz, thereby causing the output signal from inverting amplifier 304 to oscillate at the frequency of crystal 302. The output signal of the ring oscillator is divided by eight in divided-by-eight circuit 305 and then sent to phase comparator 306, which receives also the output signal from oscillator 302. Thus the control frequency of the ring oscillator is 262.144 KHz, eight times the normal frequency of crystal 302. The normal operating frequency of the ring oscillator is generally selected to be approximately the 262 Khz. The phase comparator 306 senses the phase difference between the phase of the divided-by-eight output signal from the ring oscillator and the phase of the signal from crystal oscillator 302. Phase comparator 306 provides this phase difference in an output signal on lead 306a to Vcc control circuit 307 to correct any deviation in the frequency of the ring oscillator's divided-by-eight output signal from the control frequency 32.768 Khz associated with crystal oscillator 302. Should the ring oscillator be at too low a frequency, then Vcc control circuit 307 is driven to provide a higher voltage on lead 307a to the inverter 301-15, thereby decreasing the delay time associated with this inverter and thus increasing the oscillating frequency of the ring oscillator. Alternatively, if the operating frequency of the ring oscillator is too high, then Vcc control circuit 307 provides a lower output voltage on output lead 307a, thereby increasing the delay time through inverter 301-15 and thus lowering the voltage associated with this inverter. Phase selector 308 controls the width of a pulse width modulated (PWM) output signal on output lead 310 from exclusive OR gate 309. Each of the two input leads to exclusive OR gate 309 is coupled by phase selector 308 to a tap associated with one output lead from an inverter 301-i in the ring oscillator. The output leads from the even-numbered inverters 301 are connectable one at a time to input lead 309a of exclusive OR gate 309. The output leads from the odd-numbered inverters 301 are connectable one at a time to input lead 309b of exclusive OR gate 309. The particular output leads from inverters 301-1 through 301-15 to be connected to input leads 309a and 309b of inverter 309 are selected depending upon the requirements of the power supply being driven by the PWM signal on output lead 310 from exclusive OR gate 309. Exclusive OR gate 309 will have a high output whenever its inputs are different. This happens each time a high edge or a low edge propagates through the ring oscillator past the inverters that the exclusive OR gate is attached to. Since one cycle of the ring oscillator contains both a rising edge and a falling edge, the PWM signal observed at output lead 310 of exclusive OR gate 309 will be twice the frequency of the ring oscillator. The normal frequency "f" of the ring oscillator (made-up of inverters 301-1 through 301-15) is given by the delay time ".DELTA." associated with each of the inverters. Thus if all inverters have equal delays, then the normal frequency f=1/(2n.DELTA.) where n is the number of inverters and .DELTA. is the delay time associated with each inverter. Thus the frequency is inversely proportional to the number of inverters. The period of the ring oscillator is given by 1/f. Thus if the number of inverters equals 1,000 and the delay associated with each inverter is 10.sup.-9 seconds, then the frequency is 500 Khz and the period is 2 microseconds. The various pulse widths which the system is capable of achieving are determined by the taps on the output leads of the inverters which are connected to the input leads 309a and 309b of exclusive OR gate 309. Section 1.1.2 Second Embodiment of the PWM Timing Generator FIG. 4 shows an alternative embodiment of the invention employing counters and comparators to generate a pulse width modulated signal. A five bit counter 41 (although a different number of bits can be used if desired) counts from 0 to 31 driven by a 16.7772 MHz signal. The instantaneous count from 5 bit counter 41 is sent on 5-bit bus 42 to comparators 43a and 43b, each of which compares the count to a reference count stored in it. Digital comparator 43a will store one count determined by the signals on phase select bus 44a and digital comparator 43b will store a second count determined by the signals on phase select bus 44b. The signals on phase select bus 44a and phase select bus 44b are determined by external circuitry which measures the voltage on the load capacitor and the current into the load capacitor and compares the voltage and current to reference values to determine the extent to which the charge on the load capacitor must be replenished. This is accomplished by switching power supply controller 1200, using in particular sample and hold circuit 1207, analog to digital converter 1206 and regulation control module (REG) 1204. These circuits, as well as their operation and the operation of the system are described in detail below. The output signal from digital comparator 43a toggles a D flip-flop 45a and the output signal from digital comparator 43b toggles a D flip-flop 45b. The inverting output signal from D flip-flop 45a is transferred on lead 47a to the input lead of a delay line 48a. The delay line has a length determined by bits 4-0 so as to correspond to the time taken to drive the 5-bit counter to the particular value which causes digital comparator 43a to toggle flip-flop 45a. The output signal from the delay line is transferred on lead 49a to one input lead of exclusive OR gate 49. 5-bit counter 41 continues counting after finding a match in digital comparator 43a until another match is found in digital comparator 43b. The particular value of the count in digital comparator 43b is set by bits 9-5 derived from phase select-red bus 44b as described below. The match results in input signal being sent from digital comparator 43b to D flip-flop 45b. D flip-flop 45b then produces an output signal on lead 47b, which is transmitted to the input lead of delay line 48b. Delay line 48b then produces a high level output signal on lead 49b to exclusive OR-gate 49. During the time that the output signal from delay line 48a is high and the output signal from delay line 48b is low, a pulse width modulated signal will be produced by exclusive OR gate 49 on output lead 49c. When however, the output signals on output leads 49a and 49b are the same level, exclusive OR gate 49 will produce a low level output signal on output lead 49c. Thus the output signal from exclusive OR gate 49 is phase-modulated in response to the signals on phase select-green and phase select-red buses 44a and 44b, respectively. Selecting 16.7772 MHz to drive 5-bit counter 41 causes it to cycle through its complete count 524,287 1/2 times per second. In other words, the output frequency of the signal on lead 49c from circuitry FIG. 4 is 262,144 KHz. FIG. 5 illustrates waveforms of a string of 13-series connected inverters. The top curve represents the input signal to the first inverter. The second curve represents the output signal from the second inverter. The third curve represents the output signal from the fourth inverter and the fifth, sixth, seventh and eighth curves represent the output signals from the sixth, eighth, tenth and twelfth inverters, respectively. The bottom curve represents the pulse width modulated output signal from the circuit as shown in FIG. 3 or FIG. 4. Note that, in this example, the output signal is controlled by the signals input to the series-connected inverters and the signal output from the tenth inverter. Note that the output signal is off when the signal input to the series-connected inverters and the signal output from the tenth inverter are the same amplitude and is on when these two signals are of complementary amplitudes. In one embodiment, discussed below, where the PWM signal drives a main switch of a DC/DC converter, the output current is sampled when the switch is on as shown by the dashed line and the output voltage is sampled when the switch is off as shown by the dashed line at the left hand portion of the curves. The output frequency of the pulse width modulated signal is 524,288 Hz while the frequency of change of the signals from the series-connected inverters is half this frequency over 262,144 Hz. Section 1.1.3 Discussion of Counter+Comparators Approach--Without Delay Lines--Optimization Techniques in the Implementation Digital Pulse Converter wrapper 1201 may have various implementations and include various types of interfaces to perform its functions (e.g., pulse width modulation), as described herein. For example, pulse width modulation may be performed utilizing 1) a low frequency digital phase locked loop (DPLL) voltage controlled oscillator (VCO) with inverter stages and taps (e.g., as described in reference to FIG. 3), 2) a high frequency DPLL with a counter combined with a digital comparator, or 3) a DPLL combined with a content addressable memory (CAM) to generate the required pulse width modulated signals. FIG. 36 shows an exemplary pulse width modulation implementation, which includes a pulse width generator (PWG) 2300.4 and a sequencer 2302.4, for digital pulse converter 1201. As illustrated herein, this exemplary pulse width modulation implementation is directed to a high frequency DPLL with a counter combined with a digital comparator (i.e., example 2 as listed above), with one DPLL/counter/comparator combination for each power supply to be regulated. PWG 2300.4 receives a 10-bit trigger (TRG[9:0]) signal and an 8-bit tag (TAG[7:0]) signal from sequencer 2302.4, along with a reference clock (FREF) and a reset (RST) signal. PWG 2300.4 generates a lock (PLOCK) signal, a sequencer clock (SCLK) signal, a pulse width modulation (PWM[7:0]) signal, and a clock (CLK[m:n]) signal. Sequencer 2302.4 generates the trigger (TRG[9:0]) signal and the tag (TAG[7:0]) signal and receives the global reset RST signal and a data (DATA[p:0]) signals from a control logic block such as regulation control module (REG) 1204. Sequencer 2302.4 also receives or provides control (CNTL[q:0]) signals. The tag signal allows the start and stop times of different PWM signal outputs to occur at the same trigger value (i.e., time). This allows the PWN start and stop times to slide through each other (i.e., vary independently in time relative to each other) during normal operation. As an example of a sequence control, the trigger signal values (n0, n1, n2, . . . , n15) correspond to the tag signal values (t0, t1, t2, . . . , t15), where 1023 n15> . . . >n2>n1>n0 0 (where 1023 represents a time duration from 0 to 1023 from a counter). If t1 corresponds to the start of the PWM[3] signal and t8 corresponds to the stop of the PWM[3] signal, then the pulse width of the PWM[3] signal is PWM[3]=(n8-n1).tau., where .tau..congruent.2 ns. FIG. 36A is an exemplary implementation of pulse width generator 2300.4 of FIG. 36. FIG. 36A includes a DPLL 2304.4 that generates the lock signal and an output frequency (F.sub.OUT) signal that is provided to a divider counter 2308.4 that generates the clock signal. The most significant bit of the clock signal is divided by 16 (by divider 2306.4) to provide a feedback signal for comparison to the reference clock. Divider counter 2308.4 also generates a 10-bit count (CNT[9:0]) signal that is compared to the trigger signal by a comparator 2310.4, whose output is clocked out to a PWM circuit 2314.4 via a flip flop 2312.4. PWM circuit 2314.4 also receives the tag signal and generates the PWM signal and the sequencer clock signal. An exemplary circuit implementation for PWM circuit 2314.4 is illustrated by a circuit 2316.4. FIG. 36B is an exemplary implementation of sequencer 2302.4 of FIG. 36. FIG. 36B includes a series of registers 2330.4 (which are separately referenced as 2330.4a through 2330.4p) and multiplexers 2332.4 (which are separately referenced as 2332.4a through 2332.4n) that are clocked by the sequencer clock (SCLK) signal and generate the trigger signal and the tag signal. Registers 2330.4 and multiplexers 2332.4 are controlled by a controller 2334.4, which receives the data signal and receives or provides the control signals. Controller 2334.4 operations may be performed by regulation control module (REG) 1204 or by a separate controller, such as a processor or a microcontroller, to provide the control and data sequencing logic. FIG. 36C shows an exemplary feedback control system for a PWM switching voltage regulator without a dead zone. For example, the feedback control system monitors a voltage of interest (V.sub.M) and compares it to a target voltage (V.sub.T) to generate an estimated PWM stop target (i.e., stop time) for use by controller 2334.4. FIG. 36C includes an analog-to-digital converter (ADC) 2340.4, a subtractor 2342.4, a summer 2344.4, and a register 2346.4. The voltage (V.sub.M) is digitized by ADC 2340.4 and subtracted from the voltage (V.sub.T or digital DV.sub.T) by subtractor 2342.4 and summed with an output of register 2346.4 by summer 2344.4. Register 2346.4 provides a PWM stop target (PWM.sub.ST) signal. If the voltage (V.sub.T) is greater than the voltage (V.sub.M), then the PWM stop target signal is incremented until the voltage (V.sub.T) is less than the voltage (V.sub.M), which results in the PWM stop target (PWM.sub.ST) signal to decrement. Once steady state is achieved, the control loop will continue incrementing and decrementing the PWM stop target (PWM.sub.ST) signal to minimize the difference between the voltage (V.sub.T) and the voltage (V.sub.M). This negative feedback control system relies on the fact that an increase in the PWM stop target (PWM.sub.ST) signal will cause an increase in the voltage (V.sub.M). The transient response of the control loop is small because the change in the PWM stop target (PWM.sub.ST) signal will be, for example, only one unit (e.g., .+-.2 ns) from cycle to cycle. FIG. 36D shows an exemplary feedback control system for a PWM switching voltage regulator with a dead zone. For example, the feedback control system monitors a voltage of interest (V.sub.M) and compares it to a target voltage (V.sub.T) to generate an estimated PWM stop target (i.e., stop time) for use by controller 2334.4. FIG. 36D includes converter (ADC) 2340.4, subtractor 2342.4, summer 2344.4, register 2346.4, comparators 2348.4, and a logic gate (OR) 2352.4. The voltage (V.sub.M) is digitized by ADC 2340.4 and subtracted from the voltage (V.sub.T or digital DV.sub.T) by subtractor 2342.4, with the result compared to a positive and negative dead zone target by comparators 2348.4 and 2350.4. The output of comparators 2348.4 and 2350.4 is provided to logic gate 2352.4, whose output along with comparator 2350.4 is summed by summer 2344.4 with an output of register 2346.4. Register 2346.4 provides a PWM stop target (PWM.sub.ST) signal. If the difference (i.e., the voltage (V.sub.T) minus the voltage (V.sub.M)) is less than the positive dead zone target and greater than the negative dead zone target, the PWM stop target (PWM.sub.ST) signal remains constant. Otherwise, the PWM stop target (PWM.sub.ST) signal is incremented or decremented, as required. Section 1.1.4 Discussion of PLL/RO Using CAM, Optimization Techniques in CAM Implementation FIG. 7 shows the output waveforms from the eleventh series-connected inverters shown in FIG. 6. In FIG. 6 the series-connected inverters are shown having pass transistors connected from the output of each of the inverters. For the pass transistors connecting the output signals from the odd numbered inverters to input lead 63a of exclusive OR-gate 63, each pass transistor is driven by a signal labeled as A, B, C, D, E, or F. Similarly, for pass transistors connecting the output signals from the even-numbered inverters to leads 63b to exclusive OR gate 63, each pass transistor is driven by a signal labeled G, H, I, J, or K. The pulse width modulated output signal from exclusive OR gate 63 is transmitted on output lead 63c to the load capacitor of the particular circuit being powered by the structure shown in FIG. 6. The particular combination of pass transistors to be turned on determines the width of the pulse width modulated signal output on lead 53c from exclusive OR gate 63. Turning to FIG. 7, one can see the waveform from the inverters 1 through 11. The waveform from inverter 11 is, of course, fed back in FIG. 6 to the input lead of inverter 1. FIG. 7 and FIG. 8 show waveforms for the output signals from each of the inverters 1 through 11 in FIG. 6. FIG. 7 shows the output signals for these inverters as taken straight from each inverter. FIG. 8 shows the output signals from inverters 1, 3, 5, 7, 9 and 11 taken straight from the output lead of each inverter while curves 2, 4, 6, 8 and 10 show the complement of the output signal taken from inverters 2, 4, 6, 8 and 10. FIG. 9 shows the pulse width for the various combinations of signals applied to input leads 63a and 63b of exclusive OR gate 63, respectively, throughout the pulse width of the pulse on output lead 63c from exclusive OR gate 63 is shown in the columns labeled pulse width. As can be seen from FIG. 9, only one combination of output signals from the various inverters is required to yield the five possible different pulse widths obtainable using the signals directly from the inverters. Thus the pulse widths 10, 8, 6, 4 and 2 are obtained from using on input lead 63a of exclusive OR gate 63 the output signal from inverter 1 activated by pass transistor A together with one of the output signals from inverters 2, 4, 6, 8 and 10 activated by pass transistors G, H, I, J or K. Thus pulse widths of 10 delays, 8 delays, 6 delays, 4 delays and 2 delays are obtained using these combinations. The only other combination of output signals is that which uses the output signal for inverter 11 together with the output signals from inverters 2, 4, 6, 8 and 10, which again yields pulse widths of 2, 4, 6, 8 and 10 delays. If output signals from the even-numbered inverters are inverted, then pulse widths of 1, 3, 5, 7, and 9 delays can be obtained by combining an exclusive OR gate 63 the output signal from inverter 1 with the output signal from inverters 2, 4, 6, 8 and 10, each inverted. Again, this set of pulse widths represent all possible pulse widths obtainable using inverted output signals from the even-numbered inverters together with the output signal from any one of the odd-numbered inverters. An alternative implementation for performing pulse width modulation by digital pulse converter 1201 includes a DPLL combined with a content addressable memory (CAM) to generate the required pulse width modulated signals (i.e., example 3 as listed above). Digital Pulse Converter (DPC) 1201 is a low power custom mixed-signal macro. In general, the input and output signals of DPC 1201 are digital, however separate analog power and ground signals are provided to supply an internal digital phase lock loop (DPLL) circuit used for frequency synthesis. DPC 1201 synthesizes a reference clock (32.768 khz) to produce a variety of pulses with pulse widths based on a DPC frame which starts with a count of 0 and ends with a terminal count of 1023, as illustrated in the timing diagram shown in FIG. 37. In one implementation the DPLL generates a frame clock of 524.288 KHz, yielding a frame time of 1.907 .mu.Sec. The minimum pulse width is represented by a count difference of 0 (i.e., 0% duty cycle) and the maximum pulse width by a count difference of 1024 (i.e., 100% duty cycle). The rising and falling pulse edges have a minimum resolution of 1 count, which corresponds to a real time difference of .about.1.863 ns. The pulses are used to control chip I/O output drivers within NFET driver module 1202 for external power regulation. The pulses are also used to control chip I/O input drivers within sample and hold module (SHM) 1207, with sample and hold circuits for analog to digital conversion using an on chip analog to digital converter (ADC) found within analog to digital converter 1206. DPC 1201 also generates other output signals used by other chip circuitry, for example real time clock states and synchronization pulses for regulation control module (REG) 1204, and source clocks for a Clock Generation and Enable (CKGEN) macro 1223. DPC 1201 generates pulses as shown in FIG. 37, where one DPC frame corresponds to .about.1.907 us in the timing diagram. Each pulse (i.e., a PFET pulse 2410.4, a SFET pulse 2412.4, a SMPA pulse 2414.4, and a SMPB pulse 2416.4 associated respectively with a PFET signal 2402.4, a SFET signal 2404.4, a SMPA signal 2406.4, and a SMPB signal 2408.4) generated by DPC 1201 is represented as a pair of 10-bit Grey coded numbers, which are presented to DPC 1201 through the interface of Regulation control module (REG). The Grey coded numbers are designated as Primitive numbers or simply Primitives, with a pair of Primitives associated with each pulse. The first Primitive number (i.e., a PFTS, a SFTS, a SPAS, and a SPBS in FIG. 37) in each pair indicates the offset of the leading edge of the pulse from a count of 0 and can be any integer from 0 to 1023. The second Primitive number (i.e., a PFTR, a SFTR, a SPAR, and a SPBR in FIG. 37) in each pair indicates the offset of the trailing edge of the pulse from a count of 0 and can also be any integer from 0 to 1023. The letter "S" on the end of signal parameters for the first Primitive numbers (PFTS, SFTS, SPAS, and SPBS) stands for SET and the letter "R" on the end of signal parameters for the second Primitive numbers (PFTR, SFTR, SPAR, and SPBR) stands for RESET. PFET pulse 2410.4 and SFET pulse 2412.4, shown along the ordinate of the timing diagram in FIG. 37, control Primary and Secondary NFET drivers in NFET driver module 1202 and SMPA pulse 2406.4 and SMPB pulse 2416.4 control the input sample and hold circuits in SHM 1207. The pulses shown in the diagram can be represented by 8 independent 10-bit Primitives. The eight independent Primitives are designated as follows: PFTS, PFTR, SFTS, SFTR, SPAS, SPAR, SPBS and SPBR. These primitive numbers (i.e., PFTS, PFTR, SFTS, SFTR, SPAS, SPAR, SPBS and SPBR) are stored in a special purpose, dual port content addressable memory (CAM) device in DPC 1201 and the notation for these numbers are described in detail for port descriptions below. The timing diagram in FIG. 37 shows the Primitive number set for a single pulse channel controlled by DPC 1201, however DPC 1201 can provide a number of independent pulse channels (e.g., seven independent pulse channels for external PWM-switching power conversion and an eighth independent auxiliary pulse channel which can be used for synchronization of internal or external circuitry). If DPC 1201 provides eight independent pulse channels, then a bus notation for PFET signal 2402.4, SFET signal 2404.4, SMPA signal 2406.4, and SMPB signal 2408.4 may be used to designate these independent channels as a PFET[7:0] signals 2454.4, a SFET[7:0] signals 2452.4, a SMPA[7:0] signals 2450.4, and a SMPB[7:0] signals 2448.4, respectively, as discussed below in reference to FIG. 37A. PFET[7], SFET[7], SMPA[7] and SMPB[7] refer to the auxiliary pulse channel, and the PFET[6:0] signals 2454.4 and SFET[6:0] signals 2452.4 refer to pulses which control drivers in NFET driver module 1202 to turn on and off external power FETs used for power regulation. The SMPA[6:0] signals 2450.4 and SMPB[6:0] signals 2448.4 refer to pulses which control the input sample and hold circuits in SHM 1207 for digitizing external analog voltages. It should be noted that the timing diagram shown in FIG. 37 illustrates a break before make switching algorithm between PFET signal 2402 and SFET signal 2404.4 (i.e., between the Primitive number PFTR and the Primitive number SFTS), which is generally needed for efficient power regulation. DPC 1201 for this implementation has five interfaces to communicate with five corresponding portions of switching power supply controller 1200 (i.e., IVS 1209, CKGEN 1223, regulation control module (REG) 1204, NFET driver module 1202, and SHM 1207). FIG. 37A illustrates this exemplary interface implementation for DPC 1201. The interface with IVS 1209 includes the FREF signal 2420.4. Additionally, the interface with IVS 1209 includes power and ground signals, including a VDD signal 2464.4, an AVD signal 2466.4, a VSS signal 2442.4, and an AVS signal 2444.4. The digital power and ground, VDD signal 2464.4 (e.g., 3.3 V) and VSS signal 2442.4, respectively, can be treated as global signals, whereas the analog power and ground, AVD signal 2466.4 (e.g., 3.3 V) and AVS signal 2444.4, respectively, are generally not treated as global signals. FREF signal 2420.4 is a reference clock provided to the DPLL in DPC 1201 and has a frequency and a duty cycle of about 32.768 kHz and 50%, respectively. PLOCK signal 2462.4 is a signal which is asserted (i.e., transitions to a logical high or HIGH state) and remains asserted (i.e., remains at a logical high) after the DPLL achieves and remains in a phase lock condition. Otherwise PLOCK is not asserted (i.e., a logical low or LOW state). AUX signal 2446.4 is an auxiliary signal port that is used for synchronizing circuitry external to switching power supply controller 1200. The interface with Clock Generator and Enable (CKGEN) 1223 includes various signals, including a CST[9:0] signal 2458.4, a PLLCK signal 2460.4, and a PLOCK signal 2462.4. CST[9:0] signal 2458.4 is a 10-bit Grey coded clock state bus which provides the clocks and control states to synchronize DPC 1201, regulation control module (REG) 1204, and the CKGEN macro 1223. In a standard operating mode, with SSC signal 2424.4 set LOW and FREF signal 2420.4 set to 32.768 kHz, exemplary frequencies for the CST[9:0] signals 2458.4 are given in Table 1. PLLCK signal 2460.4 is the DPLL output clock which has a frequency and a duty cycle of 524.288 kHz and 50% respectively, assuming a reference frequency for FREF signal 2420.4 of 32.768 kHz. The same frequency for the last two most significant bits of CST[9:0] signals 2458.4 is an artifact of a 10-bit Grey counter generating these frequencies. The MSB (most significant bit) and NMSB (next most significant bit), (CST[9] and CST[8], respectively, of CST[9:0] signal 2458.4) have a quadrature phase relationship to each other. TABLE 1 CST Bit Frequency kHz CST [0] 134,217.728 CST [1] 67,108.864 CST [2] 33,554.432 CST [3] 16,777.216 CST [4] 8,388.608 CST [5] 4,194.304 CST [6] 2,097.152 CST [7] 1,048.576 CST [8] 524.288 CST [9] 524.288 The interface with regulation control module (REG) 1204 includes various signals, including PD_OUT[1:0] signals 2426.4, SET[28:0] signals 2438.4, RST[28:0] signals 2440.4, ENBL[21:0] signals 2436.4, DWI[19:0] signals 2428.4, DRO[19:0] signals 2456.4, and ADW[4:0] signals 2430.4, which are input buses, and the CST[9:0] signals 2458.4, which is an output bus. Additionally, the interface includes an input signal WE 2432.4, an input signal RE 2434.4, and an output signal PLOCK 2462.4. The interface with the regulation control module (REG) 1204 is used to generate the various pulses, such as PFET pulse 2410.4 and SFET pulse 2412.4. The DWI[19:0] signals 2428.4, ADW[4:0] signals 2430.4, DRO[19:0] signals 2456.4, and input signal WE 2432.4 and input signal RE 2434.4 transfer data and control the read/write ports of the dual port CAM, discussed in further detail herein. The read port for the CAM is within DPC 1201. More specifically, the PD_OUT[1:0] signals 2426.4 are a 2 bit bus which controls the mode of operation for DPC 1201. The modes of operation are designated as Standard mode, Low Power mode, and Shut Down mode, as summarized in Table 2. When PD_OUT[1:0] signals 2426.4 are asserting the Shut Down mode, the DPLL is powered down, the CAM is in standby mode, and the rest of the digital blocks in DPC 1201 are in low power states. When PD_OUT[1:0] signals 2426.4 are asserting the Low Power mode, the DPLL is powered up and phase locked at its normal operating frequency (536,870.912 kHz), the DPLL output is divided by 16 to produce the LSB of CST[9:0] signal 2458.4 (i.e., the frequency of the CST LSB is 33,554.432 kHz), the CAM is in standby mode, and the remaining blocks of DPC 1201 are in low power states. When PD_OUT[1:0] signals 2426.4 are asserting the Standard mode, the DPLL is operating normally, the DPLL output is divided by 4 to produce the LSB of CST[9:0] signals 2458.4 (i.e., the frequency of the CST LSB is 134,217.728 kHz), the CAM is powered up and operating normally and the rest of the DPC blocks are also powered up and are operating normally. TABLE 2 Exemplary Modes PD OUT[1] PD OUT[0] MODE 0 0 Shut Down 0 1 TBD/Spare 1 0 Low Power 1 1 Standard The SET[31:0] signals 2438.4 are a 32-bit control bus which is used to independently set each output bit of DPC 1201. For example, when SET[0] of the SET[31:0] signals 2438.4 is HIGH, SMPA[0] of the SMPA[7:0] signals 2450.4 is set HIGH, and when SET[1] of the SET[31:0] signals 2438.4 is HIGH, PFET[0] of the PFET[7:0] signals 2454.4 is set HIGH. Table 3 illustrates exemplary associations between SET[31:0] signal 2438.4, the Primitive numbers, and output signals from DPC 1201. TABLE 3 Set Bits Primitive Numbers DPC Macro Outputs SET[0].about. SPAS[0], PFTS[0], SMPA[0], PFET[0], SET[3] SPBS[0], SFTS[0] SMPB[0], SFET[0] SET[4].about. SPAS[1], PFTS[1], SMPA[1], PFET[1], SET[7] SPBS[1], SFTS[1] SMPB[1], SFET[1] SET[8].about. SPAS[2], PFTS[2], SMPA[2], PFET[2], SET[11] SPBS[2], SFTS[2] SMPB[2], SFET[2] SET[12].about. SPAS[3], PFTS[3], SMPA[3], PFET[3], SET[15] SPBS[3], SFTS[3] SMPB[3], SFET[3] SET[16].about. SPAS[4], PFTS[4], SMPA[4], PFET[4], SET[19] SPBS[4], SFTS[4] SMPB[4], SFET[4] SET[20].about. SPAS[5], PFTS[5], SMPA[5], PFET[5], SET[23] SPBS[5], SFTS[5] SMPB[5], SFET[5] SET[24].about. SPAS[6], PFTS[6], SMPA[6], PFET[6], SET[27] SPBS[6], SFTS[6] SMPB[6], SFET[6] SET[28].about. SPAS[7], PFTS[7], SMPA[7], PFET[7], SET[31] SPBS[7], SFTS[7] SMPB[7], SFET[7] The RST[31:0] signals 2440.4 are a 32-bit control bus which is used to independently reset each output bit of DPC 1201. For example, when RST[0] of the RST[31:0] signals 2440.4 is HIGH, the SMPA[0] output of the SMPA[7:0] signals 2450.4 is reset LOW, and when RST[1] of the RST[31:0] signals 2440.4 is HIGH, the PFET[0] output of the PFET [6:0] signals 2454.4 is reset LOW. Table 4 illustrates exemplary associations between RST[31:0] signal 2440.4, the Primitive numbers, and output signals from DPC 1201. TABLE 4 Reset Bits Primitive Numbers DPC Macro Outputs RST[0].about. SPAR[0], PFTR[0], SMPA[0], PFET[0], RST[3] SPBR[0], SFTR[0] SMPB[0], SFET[0] RST[4].about. SPAR[1], PFTR[1], SMPA[1], PFET[1], RST[7] SPBR[1], SFTR[1] SMPB[1], SFET[1] RST[8].about. SPAR[2], PFTR[2], SMPA[2], PFET[2], RST[11] SPBR[2], SFTR[2] SMPB[2], SFET[2] RST[12].about. SPAR[3], PFTR[3], SMPA[3], PFET[3], RST[15] SPBR[3], SFTR[3] SMPB[3], SFET[3] RST[16].about. SPAR[4], PFTR[4], SMPA[4], PFET[4], RST[19] SPBR[4], SFTR[4] SMPB[4], SFET[4] RST[20].about. SPAR[5], PFTR[5], SMPA[5], PFET[5], RST[23] SPBR[5], SFTR[5] SMPB[5], SFET[5] RST[24].about. SPAR[6], PFTR[6], SMPA[6], PFET[6], RST[27] SPBR[6], SFTR[6] SMPB[6], SFET[6] RST[28].about. SPAR[7], PFTR[7], SMPA[7], PFET[7], RST[31] SPBR[7], SFTR[7] SMPB[7], SFET[7] The ENBL[23:0] signals 2436.4 are a 24-bit CAM enable bus used to independently enable the CAM match ports. The ENBL[3n] bits of ENBL[23:0] signal 2436.4 enable the SMPA[n] bits of the SMPA[7:0] signals 2450.4 and the SMPB[n] bits of the SMPB[7:0] signals 2448.4 for CAM match outputs, where n .epsilon. {0, 1, 2, . . . , 7}. The ENBL[3n+1] bits of the ENBL[23:0] signals 2436.4 enable the PFET[n] bits of the PFET[7:0] signals 2454.4 for the CAM match outputs and the ENBL[3n+2] bits of the ENBL[23:0] signals 2436.4 enable the SFET[n] bits of the SFET[7:0] signals 2452.4 for the CAM match outputs, where n .epsilon. {0, 1, 2, . . . , 7}. The CAM ENBL bus (i.e., the ENBL[23:0] signals 2436.4) and output correspondence for an exemplary implementation is given in Table 5. TABLE 5 ENBL Bus Bits DPC Macro Outputs ENBL[0] SMPA[0], SMPB[0] ENBL[1] PFET[0] ENBL[2] SFET[0] ENBL[3] SMPA[1], SMPB[1] ENBL[4] PFET[1] ENBL[5] SFET[1] ENBL[6] SMPA[2], SMPB[2] ENBL[7] PFET[2] ENBL[8] SFET[2] ENBL[9] SMPA[3], SMPB[3] ENBL[10] PFET[3] ENBL[11] SFET[3] ENBL[12] SMPA[4], SMPB[4] ENBL[13] PFET[4] ENBL[14] SFET[4] ENBL[15] SMPA[5], SMPB[5] ENBL[16] PFET[5] ENBL[17] SFET[5] ENBL[18] SMPA[6], SMPB[6] ENBL[19] PFET[6] ENBL[20] SFET[6] ENBL[21] SMPA[7], SMPB[7] ENBL[22] PFET[7] ENBL[23] SFET[7] The ENBL bits of the ENBL[23:0] signals 2436.4 are active HIGH. To enable specific CAM match ports, the corresponding enable bit is set HIGH. The ENBL[23:0] signals 2436.4 affects only the read port of the CAM and the Primitive numbers can be read from and written to the CAM through the read/write port, as described in further detail below. This feature allows the CAM to be safely updated without causing an inadvertent match during a CAM update. In addition, the ENBL[23:0] signals 2436.4 allow the capability for pulse skipping during the normal operation of the CAM. The DWI[19:0] signals 2428.4 are a 20-bit write data bus for the read/write CAM port and it is used for writing Grey coded words to the CAM. The DWI[19:0] bus 2428.4 writes to the CAM are controlled by the ADW address bus (i.e., the ADW[4:0] signals 2430.4) and the WE signal 2432.4. The DWI[9:0] bits of DWI[19:0] signal 2428.4 are allocated for the bank zero of the CAM and the DWI[19:10] bits of DWI[19:0] signal 2428.4 are allocated for bank one of the CAM. The ADW[4:0] signals 2430.4 are a 5-bit address bus used to address a single (20-bit) word in the CAM for reading or writing. For ease of implementation and in accordance with one embodiment, the CAM is split into two banks, as described in Table 6. The ADW[4:0] signals 2430.4 simultaneously addresses one 10-bit word out of 22 words in each CAM bank. For example, ADW[0] of the ADW[4:0] signals 2430.4 corresponds to the Primitive SPBS[0] in the CAM bank zero and the Primitive SPBR[0] in the CAM bank one. TABLE 6 Read/Write CAM Bank Zero CAM Bank One Port ADW Primitive Numbers Primitive Numbers ADW[0] SPBS[0] SPBR[0] ADW[1] PFTS[0] PFTR[0] ADW[2] SFTS[0] SFTR[0] ADW[3] SPAS[0] SPAR[0] ADW[4] SPBS[1] SPBR[1] ADW[5] PFTS[1] PFTR[1] ADW[6] SFTS[1] SFTR[1] ADW[7] SPAS[1] SPAR[1] ADW[8] SPBS[2] SPBR[2] ADW[9] PFTS[2] PFTR[2] ADW[10] SFTS[2] SFTR[2] ADW[11] SPAS[2] SPAR[2] ADW[12] SPBS[3] SPBR[3] ADW[13] PFTS[3] PFTR[3] ADW[14] SFTS[3] SFTR[3] ADW[15] SPAS[3] SPAR[3] ADW[16] SPBS[4] SPBR[4] ADW[17] PFTS[4] PFTR[4] ADW[18] SFTS[4] SFTR[4] ADW[19] SPAS[4] SPAR[4] ADW[20] SPBS[5] SPBR[5] ADW[21] PFTS[5] PFTR[5] ADW[22] SFTS[5] SFTR[5] ADW[23] SPAS[5] SPAR[5] ADW[24] SPBS[6] SPBR[6] ADW[25] PFTS[6] PFTR[6] ADW[26] SFTS[6] SFTR[6] ADW[27] SPAS[6] SPAR[6] ADW[28] SPBS[7] SPBR[7] ADW[29] PFTS[7] PFTR[7] ADW[30] SFTS[7] SFTR[7] ADW[31] SPAS[7] SPAR[7] The DRO[19:0] signals 2456.4 are a 20-bit read data bus for the read/write CAM port and it is used for reading Grey coded words from the CAM. The DRO[19:0] bus 2456.4 reads from the CAM are controlled by the ADW address bus (i.e., the ADW[4:0] signals 2430.4) and the RE signal 2434.4. The DRO[9:0] bits of DRO[19:0] signal 2456.4 are allocated for the bank zero of the CAM and the DRO[19:10] bits of DRO[19:0] signal 2456.4 are allocated for bank one of the CAM. The PFET[6:0] signals 2454.4 are a 7-bit bus which provides the primary power FET pulses (i.e., pulses, such as PFET pulse 2410.4) to NFET driver module 1202. The SFET[6:0] signals 2452.4 are a 7-bit bus which provides the secondary power FET pulses (i.e., pulses, such as SFET pulse 2412.4) to NFET driver module 1202. The WE signal 2432.4 is the write enable control signal for the read/write CAM port. When WE signal 2432.4 toggles HIGH, a 10-bit word is written to each bank of the CAM at the address specified by the ADW[4:0] signals 2430.4. The RE signal 2434.4 is the read enable control signal for the read/write CAM port. When the RE signal 2434.4 toggles HIGH, a 10-bit word is read from each bank of the CAM at the address specified by the ADW[4:0] signals 2430.4. The interface for NFET driver module 1202 includes various signals, including the PFET[6:0] signals 2454.4 and SFET[6:0] signals 2452.4. As discussed above, a single PFET (primary FET) and SFET (secondary FET) pulse channel is shown in the above timing diagram (FIG. 37). The interface for SHM 1207 includes various signals, including the SMPA[6:0] signals 2450.4 and the SMPB[6:0] signals 2448.4. This interface is used to control the sampling and holding of analog voltages for digital conversion by analog to digital converter 1206. As described above in accordance with one embodiment, the sample pulses SMPA (e.g., SMPA pulse 2414.4) and SMPB (e.g., SMPB pulse 2416.4) are independent from the PFET (Primary FET) and SFET (Secondary FET) pulses. Either of the SMPA[6:0] signals 2450.4 or the SMPB[6:0] signals 2448.4 can be used to control the sampling (and holding) of analog voltages in SHM 1207 for analog to digital converter 1206. The remaining signals shown in FIG. 37A and described in Table 8 include a bypass signal 2422.4 and the SSC signal 2424.4. Bypass signal 2422.4 is a test control signal used for bypassing the DPLL. When bypass signal 2422.4 is held HIGH, FREF signal 2420.4 bypasses the DPLL, but when bypass signal 2422.4 is held LOW, FREF signal 2420.4 is used for frequency synthesis. SSC signal 2424.4 is a control signal that activates spread spectrum clocking. Spread spectrum clocking is activated when SSC signal 2424.4 is HIGH; otherwise spread spectrum clocking is disabled. The spread spectrum clocking scheme implemented in DPC 1201 can be either up or down frequency spreading where the DPC frame frequency (e.g., 524.288 kHz without spread spectrum clocking) deviates from its fundamental frequency by approximately 0.5% with a modulation period of approximately 22 us. TABLE 8 Descriptive Summary of Exemplary Interface Signals Port Name Type Description Source Destination FREF Input 32.768 khz Reference Clock IVS 1209 BYPASS Input Reference Clock Bypass REG 1204 Control SSC Input Spread Spectrum Clock REG 1204 Control PLOCK Output DPLL Lock, Active HIGH CKGEN 1223 PD_OUT[1:0] Input Power Management Control REG 1204 Bus PLLCK Output DPLL Output Clock CKGEN 1223 CST[9:0] Output Count Time State Bus CKGEN 1223 REG 1204 ENBL [21:0] Input CAM Section Enable Bus REG 1204 DWI[19:0] Input CAM Read/Write Port Data REG 1204 Bus ADW [4:0] Input CAM Read/Write Port REG 1204 Address Bus WE Input CAM Read/Write Port Write REG 1204 Enable RE Input CAM Read/Write Port Read REG 1204 Enable DRO[19:0] Output CAM Read/Write Port Data REG 1204 Bus SET[28:0] Input Pulse Set Bus REG 1204 RST[28:0] Input Pulse Reset Bus REG 1204 PFET[6:0] Output Primary FET Control Bus NFET 1202 SFET[6:0] Output Secondary FET Control Bus NFET 1202 SMPA[6:0] Output Sample A Control Bus SHM 1207 SMPB[6:0] Output Sample B Control Bus SHM 1207 AUX Output Auxiliary Pulse Control IVS 1209 Port VDD Power Digital Power IVS 1209 AVD Power Analog Power IVS 1209 VSS Power Digital Ground IVS 1209 AVS Power Analog Ground IVS 1209 FIG. 37B illustrates one circuit implementation for DPC 1201 and includes a DPLL 2480.4, a spreader divider 2482.4, a Grey counter 2484.4, and a CAM module 2486.4. CAM module 2486.4 includes a modified CAM for generating PFET[6:0] signal 2454.4, SFET[6:0] signal 2452.4, SMPA[6:0] signal 2450.4, SMPB[6:0] signal 2448.4, and AUX signal 2446.4. FIG. 37C illustrates one exemplary implementation for CAM module 2486.4. CAM module 2486.4 stores, for example, 64 words (i.e., Primitives, which were discussed above), with 10-bits per word and with an address read port 2502.4 (labeled ADR[63:0]) of CAM module 2486.4 not encoded. Address read port 2502.4 provides 64 address signals, referenced collectively as ADR[63:0] signals 2508.4. The even ADR bits (ADR[0], ADR[2], . . . , ADR[62]) of ADR[63:0] signals 2508.4 are associated with CAM bank zero and the odd ADR bits (ADR[1], ADR[3], . . . , ADR[63]) of ADR[63:0] signals 2508.4 are associated with the CAM bank one, as previously discussed (e.g., in reference to ADW[4:0] signal 2430.4). ADR[63:0] signals 2508.4 are connected to 32 RS latches, which are represented by an RS latch 2504.4 (FIG. 37C), through control logic 2506.4, shown in a representative fashion in FIG. 37C. A more detailed exemplary implementation for control logic 2506.4 and RS latch 2504.4, associated with a single pulse channel at the output of CAM module 2486.4, is shown in FIG. 37D and discussed below. DPLL 2480.4 (FIG. 37B) is shown coupled to Grey counter 2484.4 (e.g., a free running 10-bit Grey Counter), with spreader divider 2482.4 situated between DPLL 2480.4 and Grey counter 2.484.4. When SSC signal 2424.4 is enabled, spreader divider 2482.4 produces spread spectrum clocking, as described above, by employing a uniform pulse swallowing technique which varies in frequency. Spread spectrum mode of operation is described below. Additionally, spreader divider 2482.4 provides the variable divide ratio for toggling between the standard and low power modes, described above for PD_OUT[1:0] signal 2426.4. The extra division provided by spreader divider 2482.4 reduces the current drawn by Grey counter 2484.4 in the low power mode. For example, as compared to a binary counter, Grey counter 2484.4 produces glitch free read operations for CAM module 2486.4. An example of operation for the implementation shown in FIG. 37B for DPC 1201 starts with DPLL 2480.4, which increments Grey counter 2484.4 (i.e., through spreader divider 2482.4) to produce the read data, identified by a DRI signal 2488.4, for CAM Module 2486.4. If the read data of DRI signal 2488.4 generates a CAM match in CAM Module 2486.4, one or more of the CAM output read address lines (i.e., ADR[63:0] signals 2508.4) of CAM Module 2486.4 becomes active, which sets or resets one or more of the 32 RS latches (i.e., RS latch 2504.4) to produce the output pulses on the PFET[7:0] signals 2454.4, SFET[7:0] signals 2452.4, SMPA[7:0] signals 2450.4 and SMPB[7:0] signals The 32 RS latches (represented by RS latch 2504.4) are organized into eight pulse channels. The 4 pulses within a pulse channel are completely independent as described earlier And the eight independent Primitive numbers (one set of eight numbers for each pulse channel) are Grey coded and written to specific address locations in the CAM of CAM module 2486.4 regulation control module (REG) 1204. The address locations for the Primitive numbers are given above in reference to ADW[4:0] signal 2430.4. CAM Module's 2486.4 logic that is associated with one pulse channel (e.g., given by a PFET[n] signal 2512.4, an SFET[n] signal 2516.4, an SMPA[n] signal 2510.4, and an SMPB[n] signal 2514.4, where n .epsilon. {0, 1, 2, . . . , 7}) is shown in detail in FIG. 37D. Eight independent CAM ADR lines (e.g., ADR[8n], ADR[8n+1], ADR[8n+2], ADR[8n+3], ADR[8n+4], ADR[8n+5], ADR[8n+6] and ADR[8n+7]) from the ADR[63:0] signals 2508.4 are shown controlling four RS latches (separately referenced as RS latches 2504.4(1) through 2504.4(4)) of RS latch 2504.4. The control circuitry for the ENBL[23:0] signals 2436.4, which are separately referenced as enable control logic 2506.4(1) of control logic 2506.4, is also shown in detail in FIG. 37D. The ENBL[3n+1] signals and ENBL[3n+2] signals, of the ENBL[23:0] signals 2436.4, control RS latches 2504.4(2) and 2504.4(4) for the PFET[n] signals 2512.4 and SFET[n] signals 2516.4, respectively, and the ENBL[3n] signals of the ENBL[23:0] signals 2436.4 controls RS latches 2504.4(1) and 2504.4(3) for the SMPA[n] signals 2510.4 and SMPB[n] signals 2514.4, respectively. Table 5, discussed above, provides additional details regarding the ENBL[23:0] signals 2436.4. The control circuitry for the SET[31:0] signals 2438.4 and the RST[31:0] signals 2440.4, which are-separately referenced as set/reset control logic 2506.4(2) of control logic 2506.4, is also shown in detail in FIG. 37D. The SET[31:0] signals 2438.4 and RST[31:0] signals 2440.4 allow direct control of RS latch 2504.4 (e.g., RS latches 2504.4(1) through 2504.4(4)) at the output of CAM Module 2486.4). In the low power mode, this interface is used in conjunction with the ENBL[23:0] signals 2436.4 by logic in regulation control module (REG) 1204 to generate the ADC samples and power regulation pulses needed for operation in this mode. Using these control signals, regulation control module (REG) 1204 can take direct control of RS latch 2504.4 to avoid hazard conditions (e.g., preventing the set (S) and reset (R) inputs to each latch from being active simultaneously). As shown in FIG. 37C, a CAM 2494.4 is a dual-port memory device with one read/write port 2496.4 (associated with the DWI[19:0] signals 2428.4, ADW[4:0] signals 2430.4, WE signal 2432.4, RE signal 2434.4, and DRO[19:0] signals 2456.4) and one read port 2498.4 (associated with the DRI signals 2488.4 and ADR[63:0] signals 2508.4). The same Primitive number can be written to two or more address locations in CAM 2494.4, which will cause multiple matches on the ADR[63:0] signals 2508.4 (i.e., the CAM read address lines) when the matching data is presented to read port 2498.4 (through the DRI signals 2488.4) of CAM 2494.4 by Grey Counter 2484.4. The multiple matches allow two or more output edges to coincide. Regulation control module (REG) 1204 synchronizes the writes to CAM 2494.4 to avoid the generation of inadvertent glitches on the various pulse channels. When key independent pulse edges (i.e., master edges) change from one DPC frame of DPC 1201 to the next, regulation control module (REG) 1204 re-computes the dependent pulse edges (i.e., slave edges) and updates CAM 2494.4 accordingly. The master edges correspond to the Primitives PFTS[n], PFTR[n], SFTS[n], and SFTR[n], where n .epsilon. {0, 1, . . . , 7}. All other edges are either slave edges or auxiliary edges. If a master edge is moved from its position (Grey coded count) in the current DPC frame of DPC 1201 to a different position in the next frame, the slave edges related to the specific master edge are re-computed and written to CAM 2494.4 by regulation control module (REG) 1204 for use in the next frame. Regulation control module (REG) 1204 provides the computations, Grey coding, and CAM write coordination required to perform these tasks efficiently and without hazards. The information necessary to compute the slave edges from the master edge information is contained within regulation control module (REG) 1204, and this information does not generally change from one DPC frame of DPC 1201 to the next. For example, the slave edge information necessary to calculate the Primitive data SPAS and SPBS edges for each channel can be provided as a single 10-bit binary constant (or pulse width), which is used by regulation control module (REG) 1204 to compute and Grey encode a new Primitive SPAS value if a Primitive PFTS value changes or (more likely) to compute and Grey encode a new Primitive SPBS value if a given Primitive PFTR value changes. The master edge information provided by regulation control module (REG) 1204 can change from one DPC frame of DPC 1201 to the next. Regulation control module (REG) 1204 provides this information as pairs of 10-bit Grey coded numbers comprised of two offsets from a DPC 1201 frame initial count of zero. One offset corresponds to the SET input of one of the RS latches (i.e., RS latch 2504.4) at the output of CAM module 2486.4 and the other offset corresponds to the RESET input of the RS latch. As mentioned above, read port 2498.4 of CAM 2494.4 (associated with DRI signal 2488.4) is buried within DPC 1201, as illustrated in FIG. 37B and FIG. 37C. The ENBL[23:0] signals 2436.4 affects only the read port of CAM 2494.4 and is used for the multiple functions described above. If a specific ENBL bus bit of the ENBL[23:0] signals 2436.4 is held LOW, for example ENBL[0] bit, the read address section corresponding to the ENBL[0] bit is disabled and any data match occurring in the corresponding disabled section (e.g., the Primitives SPAS[0], SPAR[1], SPBS[0] and SPBR[0]) will not produce a match. However, if the same data occurs in another read address section of CAM 2494.4, which is not disabled, the match will occur. Because the ENBL[23:0] signals 2436.4 only affects the read port of CAM 2494.4, read/write port 2496.4 is not affected. Therefore, reads and writes to CAM 2494.4 through read/write port 2496.4 can take place unimpeded. This capability can be used in conjunction with the PFET[7:0] signals 2454.4 or SFET[7:0] signals 2452.4 to safely update the Primitive numbers in CAM 2494.4 and avoid the inadvertent generation of pulse glitches. One possible update sequence is shown in the timing diagram of FIG. 37E for updating the Primitive SFTR[0] in CAM 2494.4. The Primitive SFTR[0] update to CAM 2494.4 starts with the rising edge of an SFET[0] bit of the SFET[7:0] signals 2452.4. At the rising edge of the SFET[0] bit, the SFTS[o] Primitive match has already occurred. Regulation control module (REG) 1204 detects the rising edge of the SFET[0] bit and disables the required CAM section of CAM 2494.4 one regulation control module (REG) 1204 clock cycle later by setting an ENBL[2] signal LOW. Note that this does not present a problem for a PFET[0] pulse of the PFET[7:0] signals 2454.4, because the rising and falling edges of that pulse have already occurred. After the CAM section of CAM 2494.4 is disabled, regulation control module (REG) 1204 enables a CAM write by toggling WE signal 2432.4 HIGH. Because the ADW[4:0] signals 2430.4 (i.e., the read/write address port ADW) has been set to address location 2, which corresponds to the Primitive SFTR[0] as shown in Table 6, the new Primitive for SFTR[0] is written to the CAM address location 2 of CAM 2494.4. Regulation control module (REG) 1204 then re-activates the section by setting the ENBL[2] bit HIGH and the new falling edge of the SFET[0] pulse of the SFET[7:0] signals 2452.4 occurs at the new SFTR[0] Primitive value when the CAM match occurs as indicated by the falling edge of the SFET[0] pulse. Changing some Primitives has more of an effect on other Primitives than the example given in reference to FIG. 37E. Because of the dependencies discussed herein, if the Primitive PFTR is changed, the Primitives SPBS, SFTS, and SFTR may need to be recomputed, G |